1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method for a metal interconnect having an inner air spacer, applicable to multilevel interconnect technologies.
2. Description of Related Art
In order to build an integrated circuit, it is necessary to fabricate many active devices on a single substrate. Initially, each of the devices must be electrically isolated from the others, and specific devices must subsequently be interconnected in fabrication sequence so as to implement the desired circuit function, such as processing data in a microprocessor.
The data processing capability of the microprocessor has been extended to respond to more powerful and sophisticated program software, while such extension inevitably requires an increase in the operation speed of a metal oxide semiconductor (MOS) device. The operation speed of the MOS device is increased by creating an environment having a low dielectric constant between adjacent metal lines in a multilevel interconnect structure, while such environment is essential for reducing a cross-talk error and a capacitance between the metal lines. Since air was known to have a very low dielectric constant (about 1), an optimal dielectric constant for reduction of cross-talk and adverse capacitive coupling in polysilicon and metal interconnect, an air gap structure formed between the metal lines has been adopted in most interconnect process. As a result, the circuit speed is improved and logical cross-talk errors are avoided. FIGS. 1A and 1B are schematic diagrams illustrating a conventional method of fabricating the air gap structure.
Referring to FIG. 1A, a dielectric layer 100 is provided above a device layer (not shown), wherein the dielectric layer 100 has metal plugs 102 formed therein. Metal lines 104 are formed on the dielectric layer 100 to cover the metal plugs 102. As a result, the metal lines 104 are not in direct contact with the metal layer (not shown) below the dielectric layer 100, except through the metal plugs 102 in order to prevent an electrical short.
Referring to FIG. 1B, an inter-metal dielectric (IMD) layer 106 is formed to cover the metal lines 104 and the dielectric layer 100 by a method, such as plasma enhanced chemical vapor deposition (PECVD). The IMD layer is usually made of material, such as silicon dioxide, due to its low dielectric constant (about 3.9). According to the method taught by such prior art, one skilled in the art would expect to form a void or air gap 108 between two adjacent metal lines 104, as shown in FIG. 1B. However, the air gap 108 formed as such, does not effectively reduce the dielectric constant between the metal lines 104. Moreover, the air gap 108 can only be formed between metal lines 104 that are in a denser distribution. Therefore, other materials, such as hydrogen silsesquioxane (HSQ) which provides a lower dielectric constant (about 2.9-3.0) and offers a better topographical planarity is needed to reduce the dielectric constant between the metal lines.
However, when HSQ is applied to interconnect technology, particularly for gap filling, it was found that its dielectric constant became undesirably high as a result of subsequent processing. For example, after the deposition of the silicon oxide layer by PECVD, the dielectric constant of the deposited HSQ layer undesirably increased from about 2.9 to about 3.6. This rise in dielectric constant is believed to be a result of the oxidation of the top surface of the HSQ due to exposure to an oxygen-containing ambient at an elevated temperature. The undesirable increase in the dielectric constant of the HSQ layer adversely impacts the intrametal capacitance and, therefore circuit speed.